Package 3D Interconnection and Method of Making Same

ABSTRACT

A method of manufacturing an integrated circuit (IC) package is provided. The method includes stacking an interposer substrate and a device structure, the interposer substrate having a first plurality of contact members formed on a first surface of the interposer substrate and the device structure having a second plurality of contact members that are exposed at a surface of the device structure, and laminating the interposer substrate and the device structure such that the first plurality of contact members are physically and electrically coupled to the second plurality of contact members. The interposer substrate is configured such that a circuit member mounted to a second surface of the interposer substrate is electrically coupled to the second plurality of contact members.

CROSS REFERENCE TO RELATED APPLICATIONS

This application is a continuation in part of U.S. Non-provisional application Ser. No. 13/174,066, filed Jun. 30, 2011, which claims the benefit of U.S. Provisional Appl. No. 61/448,880, filed Mar. 3, 2011, both of which are incorporated by reference herein in their entireties.

BACKGROUND

1. Field

Embodiments described herein generally related to integrated circuit (IC) device packaging technology.

2. Background

Die-up plastic ball grid array packages were first introduced by Motorola and were called Overmolded Plastic Pad Array Carriers (OMPAC) (See, B. Freyman, and R. Pennisi, “Overmolded Plastic Pad Array Carriers (OMPAC): A Low Cost, High Interconnect Density IC Packaging Solution for Consumer and Industrial Electronics”, Electronic Components and Technology Conference, IEEE, pp. 176-182, 1991). Commonly known as a PBGA package, the plastic ball grid array package features a plastic printed circuit board (substrate) typically made of BT (Bismaleimide Triazine) resins or FR4 materials.

Conventional PBGA packages have the drawbacks of (1) poor thermal performance, (2) no EMI protections, (3) thick top mold and overall package profile height, (4) small ratio of die-to-package size since the mold cap must be clamped to the package substrate for molding, and (5) large package body size. Both the resin substrate and the plastic molding compound materials have low thermal conductivity values (around 0.19˜0.3 W/m·° C. for BT or FR4 type substrate and 0.2˜0.9 W/m·° C. for the molding compound). Since the die is surrounded entirely by materials with poor heat conduction properties, the heat generated on the IC die is trapped within the PBGA package. The temperature of the IC die has to rise to very high values above the environment temperature in order to release the trapped heat to the environment.

Both the resin substrate and the plastic molding compound materials are transparent to electromagnetic radiation. Consequently, electromagnetic radiation generated from the IC device will escape from the package and enter the electronic system and interfere with other electronic components. The IC device is also unprotected from electromagnetic radiation emitted from other components inside as well as outside the electronic system.

The mold thickness of the Joint Electron Device Engineering Council (JEDEC) standard PBGA packages is 1.17 mm. At a mold thickness of 117 mm, the overall heights of PBGA packages commonly are in the range of 1.5 mm˜2.5 mm. For mobile applications such as hand-held communication devices (cell phones, global positioning devices, watch-size communication devices, etc.), mobile multimedia (video/audio) players, wireless personal area networking devices such as Bluetooth headset, and flash memory devices such as memory cards, paper-thin packages are desirable to enable small electronic devices for these applications.

A mold chase with multi-cavity mold caps is used for mold encapsulation of JEDEC standard PBGA packages. Each individual substrate unit in a substrate strip or panel has a corresponding mold cap for molding using thermoset molding epoxy. This is necessary in order to clamp the mold chase to the package substrate peripheral in a transfer molding process. The periphery of the substrate top surface is exposed (not covered by the molding compound). Both the IC die and wirebond interconnections from the die edge to the package substrate must be placed within the mold cavity. Additionally, the IC die and the wirebond must be kept at a sufficient distance away from the inner walls of the mold cavity to allow mold flow and avoid wire sweeping. Consequently, the size of the IC die is confined by the size of the mold cap (mold cavity). For a given size of substrate, the allowed maximum size of the die is substantially smaller than the size of the substrate.

Conventional PBGA packages are typically large in body size, ranging from 19 mm×19 mm and above. A large package size is undesirable for mobile applications where bulky electronic components make for bulky devices. To reduce package size, chip scale packages have been developed where the size of the IC die is very close to the size of the package. In addition to the smaller solder balls and smaller ball pitch used for a fine pitch ball grid array (FBGA) package, the mold thickness is reduced to 0.25 mm˜0.7 mm. The molding compound covers the entire top surface of FBGA package that enables the increase of die size to substrate size ratio.

Dreiza et al. reported stacked packages using wirebonded bottom PSvfBGA (package stackable very thin fine pitch BGA) (M. Dreiza, A, Yoshida, J. Micksch, and L. Smith, Implement Stacked Package-on-Package Designs, http://www.eetasia.com/ART 8800379158_(—)480100_TA_db7b00bf.HTM). The package-to-package interconnection is facilitated by mounting the top ball grid array (BGA) package to the substrate of the bottom package. The bottom package has exposed land pads on the substrate top surface which provide contact with the solder balls on the top BGA package. The exposed solder ball land pads are located along the periphery of the substrate top and surround the package molding compound. The top package can be attached to the bottom package using conventional reflow surface mount processes. The PSvfBGA provides the added advantage of reducing overall package stack height by placing the IC die of the bottom package within a window opening in the substrate center.

Because the solder ball land pads on the bottom package substrate top must be exposed for stacking the top package, the IC die of the bottom package must be encapsulated with a mold cavity (mold cap) to define the extent of the mold and prevent the mold compound from covering or contaminating the ball pads. Consequently, the die size in the bottom package can not be too large in order for both the die and bond wires to fit into the mold.

Improvements in EMI shielding have been made for BGA type of IC packages. U.S. Pat. No. 7,432,586, issued Oct. 7, 2008, and commonly owned with the present disclosure, proposes a metal shield integrated into a die-up wire bond ball grid array (BGA) package for both EMI isolation and thermal improvement. The disclosure of the '586 patent is incorporated herein by reference in its entirety as though set forth in full below. In the design disclosed in the '586 patent, an IC die is enclosed inside a top metal structure and a bottom metal structure. The top metal structure is shaped like an inverted cup. The top metal structure is in contact with a flat metal structure at the bottom portion of the mold body. An IC die is mounted on the flat bottom metal structure. Ambient EMI radiations are blocked by the grounded top and metal structures from interfering with the operation of the IC die. This design provides an enclosed metal box, a Faraday cage, for EMI shielding within a wire bond BGA package. For a flip chip die, however, the metal box structure disclosed in the '586 patent cannot provide an interconnection between the IC die and the substrate.

Ideally in package-on-package devices, both the bottom and top packages in the package stack are the same size and type of packages with exactly the same structure (same size of die, same substrate or die carrier design and structure, etc.) in order to minimize stress match between packages. However, interconnections between stacked wirebond packages are most easily made between the package substrates. To provide a vertical package interconnection, the bottom package substrate is partially exposed along the substrate periphery. A transfer mold process with a mold cap cavity smaller than the substrate size must be used. This requirement to partially expose the substrate top surface for package-to-package interconnection purposes limits the bottom package to a PBGA package, or package with similar features. In order to minimize stress mismatch, the top package is also limited to a transfer molded BGA package such as a PBGA package. For an overmold package such as a fine pitch ball grid array (FBGA), it can only be used for the top package because the FBGA substrate top is entirely covered by the mold compound.

Moreover, stacking of FBGA packages can be desirable to reduce the overall footprint size of stacked packages and to reduce overall stacking height (or increase the number of packages in a package stack for a given height) by taking advantage of chip scale design feature and thin mold chase of the FBGA package.

BRIEF DESCRIPTION OF THE DRAWINGS/FIGURES

The accompanying drawings, which are incorporated herein and form a part of the specification, illustrate the present invention and, together with the description, further serve to explain the principles of the invention and to enable a person skilled in the pertinent art to make and use the invention.

FIG. 1 illustrates a view of a vertical/3-dimensional package interconnection with an interposer substrate.

FIGS. 2A-2D illustrates views of various embodiments of an interposer substrate.

FIG. 3A illustrates a view of a further embodiment of a vertical/3-dimensional package interconnection with an interposer substrate having a truncated mold top.

FIG. 3B illustrates a view of a further embodiment of a vertical/3-dimensional package interconnection with an interposer substrate having drilled mold top contact pads.

FIG. 4A illustrates a view of an embodiment of a System in Package (SiP) having a molded interposer substrate.

FIG. 4B illustrates a view of an embodiment of a SiP having a partially exposed interposer substrate.

FIG. 4C illustrates a view of an embodiment of a SiP having an interposer substrate which is substantially the same size as the bottom package.

FIG. 5A illustrates a view of an embodiment having EMI shield and system partitioning with a ground/power bus along an outer row of a molded BGA for EMI shield and system partitioning.

FIG. 5B illustrates a view of an embodiment having EMI shield and system partitioning with a ground/power bus along an inner row of a molded BGA for EMI shield and system partitioning.

FIG. 5C illustrates a view of an embodiment having EMI shield and system partitioning with signal partitioning.

FIG. 6 illustrates an example flowchart for manufacturing IC packages, according to exemplary embodiments of the present invention.

FIG. 7 illustrates a view of an IC die attached to a surface of a substrate.

FIG. 8 illustrates a view of an IC die and conductive elements formed on a surface of a substrate.

FIG. 9 illustrates a view of a plurality of solder balls, an IC die, and a first surface of a substrate encapsulated in mold compound.

FIG. 10 illustrates a view of solder balls exposed above a mold top surface.

FIGS. 11-12 illustrate steps in forming through mold vias (TMV) using solder paste.

FIGS. 13 and 14 illustrate views of devices after removal of layers of a mold compound.

FIG. 15 illustrates a view of mold compound having holes that expose respective solder bails.

FIGS. 16 and 17 illustrate views of interposer substrates having conductive posts and contact pads, respectively.

FIGS. 18-22 illustrate views of interposer substrates coupled to a substrate.

FIG. 23 illustrates a view of a component attached on a surface of an interposer substrate.

FIG. 24 illustrates a view of a package interconnection embodiment with multiple interposer substrates.

FIG. 25 illustrates a view of an IC package having an interposer substrate.

FIG. 26 illustrates an example flowchart for manufacturing IC packages, according to exemplary embodiments of the present invention.

FIG. 27 illustrates a cross-sectional view of an interposer substrate.

FIG. 28 illustrates a top view of a strip of interposer substrates.

FIG. 29 schematically illustrates coupling a plurality of solder balls to solder balls of a device structure.

FIG. 30 illustrates a top view of a device structure.

FIG. 31 illustrates a view of an IC package having an interposer substrate.

FIG. 32 illustrates a cross-sectional diagram of a device structure stacked on a substrate interposer.

FIG. 33 illustrates a strip of device structures.

The present invention will now be described with reference to the accompanying drawings. In the drawings, like reference numbers indicate identical or functionally similar elements. Additionally, the left-most digit(s) of a reference number identifies the drawing in which the reference number first appears.

DETAILED DESCRIPTION Introduction

It is noted that references in the specification to “one embodiment”, “an embodiment”, “an example embodiment”, etc., indicate that the embodiment described may include a particular feature, structure, or characteristic, but every embodiment may not necessarily include the particular feature, structure, or characteristic. Moreover, such phrases are not necessarily referring to the same embodiment. Further, when a particular feature, structure, or characteristic is described in connection with an embodiment, it is submitted that it is within the knowledge of one skilled in the art to effect such feature, structure, or characteristic in connection with other embodiments whether or not explicitly described.

Furthermore, it should be understood that spatial descriptions (e.g., “above”, “below”, “left,” “right,” “up”, “down”, “top”, “bottom”, etc.) used herein are for purposes of illustration only, and that practical implementations of the structures described herein can be spatially arranged in any orientation or manner.

The embodiments described herein provide a methodology for package vertical interconnection interconnections through an embedded vertical interconnection structure within an IC package. The package vertical interconnection structure is a molded ball grid array or molded conductor posts as disclosed in U.S. patent application Ser. No. 11/589,120, filed Oct. 30, 2006 by Zhao and Khan, and commonly assigned with the present disclosure; the disclosure of the '120 application is incorporated herein by reference in its entirety, as though set forth in full below. The molded vertical interconnect elements are partially exposed through the top surface of the package mold compound, forming contact pads on the package top. The contact pads for interconnection provide landing pads for electrical interconnection on top of the mold compound. A printed circuit board, called an interposer substrate herein, is connected to the contact pads on the package mold top. The interposer substrate has one or more conductor posts or solder bumps or balls on its bottom as interconnect terminals. The through the mold compound interconnection structure of the bottom package provides direct interconnection between the package bottom substrate and the interposer substrate on the package mold top. The interposer substrate provides an interface structure for package-to-package vertical interconnection. The interposer substrate top has contact pads for interconnection with other surface mountable components such as ASICs and memory device packages including flip chip and wire bond BGAs, passive components such as capacitors, inductors, electromagnetic coupling baluns, electromagnetic radiators, resistors, etc.

The disclosure is related to (1) a system in package (SiP) technology, (2) a package-on-package (PoP) vertical interconnection technology of two or more bail grid array (BGA) packages, (3) a low profile package PoP design, (4) enabling stacking of chip-scale packages, (5) reduction of electromagnetic interference (EMI) and providing EMI shielding, (6) thermal performance enhancement technologies for IC packages, (7) electrical performance enhancement technologies for IC packages, and (6) high speed communication applications.

One or more integrated circuit (IC) dies may be attached directly to the top surface of the printed circuit substrate using epoxy. Wire bonds can be used to electrically connect an IC die to the printed circuit on the substrate. A matrix of solder balls is mounted on the bottom side of the substrate.

The IC die and the wire bonds are protected from the environment by a plastic molding compound which encapsulates both the IC die and the wire bonds and covers the center region on the top surface of the substrate. The periphery of the substrate top surface can be exposed.

Conventional IC die encapsulation processes such as dam-and-fill (glob top), mold cap injection molding (transfer molding), strip or panel over-molding (mold compound covers the edges of package substrate) can be used in the proposed designs for both top and bottom packages. The interconnection structure can be used for wire bond ball grid array (BGA) packages, such as fine pitch PGA (FBGA) and plastic BGA (PBGA), and flip chip packages. The disclosed structure can also be used for package stacking of land grid array (LGA) packages, leadframe and flip chip packages stacking on BGA package, and their combinations.

Stacking of packages on top of one another requires electrical interconnections between the external terminals of the top and bottom packages. Overmolded area array packages such as FBGA and LGA packages do not have electrical signal interconnect terminals on the package top surface. The same problem exists for certain type of leadframe packages such as no-lead quad flat package (QFN, also known as MLP, MLF, and LPCC packages) as well as thin array plastic package (TAPP) (see, e.g., U.S. Pat. No. 7,482,690, issued Jan. 27, 2009, titled “Electronic Components Such As Thin Array Plastic Packages And Process For Fabricating Same.” Consequently, these packages cannot have other packages stacked on their top.

A solution using truncated solder balls molded within the package molding compound and extended to the top of the mold on the package top provides electrical contact pads on the mold top with other packages. Because the solder balls can be embedded within the mold of the bottom package, the package-to-package interconnect contact pads do not have to be placed outside the mold of the bottom package as required in the stacked packages. Therefore, the footprint of the stacked packages can be minimized. In mobile applications such as cell phones, hand-held video and audio players, smaller footprint size of system in package (SiP) usually translates into smaller application devices. Conductor posts through the package mold can also be used for the bottom package contact pads with top mounted component.

However, contact pads provided directly on the bottom package mold top have the drawback of a large variation of pad diameter, pad placement location accuracy, and pad-to-pad pitch. These problems made it difficult to mount components requiring a high precision of interconnect contact pads on the bottom package. For example, fine pitch components with electrical contact pitch smaller than 0.40 mm may be difficult to mount on top of the bottom package mold due to high yield loss caused by short or open at the electrical contact terminals. A solution to this problem is to use an interposer substrate between the bottom package and top mounted components. The interposer substrate can have interconnect terminals or pads on its bottom with size and terminal-to-terminal pitches suitable for the interconnection with the contact pads on the bottom package mold top. The interposer substrate also has electrical interconnect contact pads on its top for receiving surface mountable components such as IC packages and passive components. Interconnect terminal pitches are typical larger on the interposer substrate bottom than the pitches of contact pads on the interposer substrate top to accommodate lower manufacturing control tolerance for contact pads on the bottom package. From an interconnect pitch standpoint the interposer substrate acts as a transition from a larger interconnect pitch on the bottom to a smaller interconnect pitch on the top. It is also possible to have a smaller interconnect terminal pitch on the interposer substrate bottom and a larger interconnect terminal pitch on top. The same interconnect terminal pitches on both sides of the interconnect substrate are also possible with the interposer substrate. In essence, the interposer substrate is an interconnect structure that facilitates vertical interconnection between packaged components.

Because the solder balls are placed directly on the contact pads of the bottom die, the electrical interconnection path length from the IC die in the bottom package to the IC die in the top package is substantially reduced. Consequently, the impedance of the interconnection can be reduced substantially and higher speeds for signal transmission between the IC dies can be realized.

Disclosed herein are structures and implementations of package-to-package direct interconnection structure embedded within a plastic mold compound and exposed on the plastic mold top surface. Applications of the interconnection contact pads on molded IC chips for package stacking and various structures of stacked packages are also disclosed herein.

FIG. 1 illustrates a view of the structure of a vertically integrated IC package 100. IC package 100 has a first or bottom package substrate 102. First substrate 102 had a first or bottom surface 104 and a second or top surface 106. Solder balls 108 are fixed to first surface 104 in physical and electrical contact with second surface 106. Solder balls 108 are attached to pads (not shown) on first surface 106 of first package substrate 102. Solder balls 110 are attached to pads (not shown) on second surface 106 of substrate 102.

IC package 100 further includes a second or interposer substrate 112 which is spaced from first substrate 102. Interposer substrate 112 has a first or bottom surface 114 and a second or top surface 116. One or more, typically a plurality, of conductor posts or pillars 118 are physically and electrically connected to first surface 114 of interposer substrate 112. Conductor posts 118 physically and electrically mate with corresponding contact pads (not shown) on first substrate 102 via solder balls 110. In another embodiment, one or more of conductor posts 118 can be replaced with small solder balls or other types of interconnection elements, as would be appreciated by those skilled in the art based on the description herein. Conductor posts 118 can be formed out of copper, aluminum, or other materials used to form conductive interconnection elements, as would be appreciated by those skilled in the relevant art based on the description herein. A mold compound 120 is interposed between first and second substrates 102 and 112.

Solder balls 110 may be molded within molding compound 120, as disclosed in U.S. Pat. No. 7,714,453, issued May 11, 2010, titled “Interconnect Structure And Formation For Package Stacking Of Molded Plastic Area Array Package,” and commonly assigned with the present disclosure. The disclosure of the '453 patent is incorporated herein by reference in its entirety as though set forth in full below.

As described in more detail below, after molding and post mold curing, solder balls 110 may be entirely encapsulated in the molding compound 120. The top of the solder balls could also be partially exposed if the solder ball height is at or very close to the thickness of the mold cap. A top layer of molding compound 120 is subsequently removed and, in the process, the top of solder balls 110 are truncated simultaneously to expose the circular pads formed by the truncated solder spheres that are embedded in mold compound 120. Other methods, such as mechanical drilling, chemical etching, etc., as disclosed in the '120 patent, can also be used to expose solder balls 110. In addition, laser ablation can also be used to remove mold compound 120 and expose solder balls 110 to make interconnect contact pads on bottom package top surface 106. These exposed circular pads provide contact terminals on the mold top.

The second or top surface 116 of interposer substrate has one or more, typically a plurality, of contact pads (not shown) on its surface. These contact pads can be used to connect electronic components 122 for package-to-package electrical interconnections such as package stacking to form a package-on-package (PoP) stack. Multiple electronic components, including packaged IC devices, inductors, capacitors, and resistors can all be attached to the package mold top on these exposed pads.

There are various methods to make contact pads OD the bottom package mold top surface 106 through exposing the top of the molded solder balls 110. Examples of implementation by removing a layer of package mold top and to truncate and expose the embedded solder balls are illustrated in the '120 application. An advantage of removing an entire layer of package mold compound 120 is that the contact pads formed are on the same surface as the top surface of mold compound 120. Conductor posts 118 can be used as the terminals to contact bottom package substrate 102 through interconnect solder balls 110. Manufacturing tolerances for both the bottom package warpage and interposer substrate 112 can also be increased and still allow the interconnection contact when the contact pads are on the top plane of the bottom package. When the bottom package mold top contact pads are below the top plane of mold compound 120, longer contact terminals on interposer substrate 112 are required in order to reach the contact pads. Less warpage tolerances for both bottom package and interposer substrate 112 are allowed to ensure contact between the interposer substrate terminals and the contact pads below the bottom package mold top surface.

Different types of device packages (flip chip, FBGA, etc.) can be mounted on the interposer substrate top surface 116. More than one package can be mounted on the interposer substrate. Antenna(s), antenna array(s)/matri(ces), baluns for wireless applications, and passive components such as capacitors, inductors, and resistors can be mounted on interposer substrate 112.

A gap (standoff) between interposer substrate 112 and first substrate 102 the top surface of mold compound 120 is allowed but not preferred. Contaminants can be trapped in this gap. These contaminants could cause shorting between adjacent contact pads on the mold top or between adjacent conductor posts 118.

An air gap between interposer substrate bottom surface 114 and the top surface of mold compound 120 can be filled with adhesive material preformed on bottom surface 114 of interposer substrate 112. For example, a layer of heat activated adhesive can be formed (coated or laminated) on bottom surface 114 of the interposer substrate 112. During the manufacturing process of the interposer substrate-to-bottom package attachment, the adhesive layer is bonded to the bottom package mold top and fills the gap between interposer substrate 112 and the top surface of mold compound 120. Examples of a suitable adhesive film can be the Tomoegawa X adhesive or the Toray 8300 adhesive.

Interposer substrate 112 can be either stiff or flexible and can have either single conductor layer or multiple conductor layers. The conductor pillars 118 on the bottom surface 114 of the interposer substrate can be made of copper. Conductive posts 118 are exposed. A method of making copper pillars on a substrate is shown in published international application WO2006/028090, published Mar. 16, 2006, and titled “Member for Interconnecting Wiring Films and Method for Producing the Same.”

FIGS. 2A-2D illustrate views of various embodiments of elements used to couple interposer substrate 112 to first substrate 102. To enhance surface wetting during interposer substrate attachment to the bottom package contact pads, the tip of conductor posts 118 (see FIG. 2A) on bottom surface 114 can be plated with a layer 202 of solder, tin, tin and silver alloy, or other metal of non-metal materials (see FIG. 2B). Layer 202 can help to reduce oxidation and promote fusion between the conductor posts 118 on interposer substrate 112 and the contact pads on the bottom package mold top. A solder cap 204 (see FIG. 2( c)) can also be formed on the tip of conductor posts 118, to promote fusion of the conductor posts 118 and the contact pads on bottom package mold top surface.

Small solder balls 206 (see FIG. 2D) or solder bumps can be attached directly on the bottom of the interposer substrate 112 to replace the copper pillars 118. An interposer substrate 112 with solder bumps/balls 206 attached on bottom surface 114 is called a bumped substrate herein. The solder balls 206 can be attached to the interposer substrate bottom surface 114 using the same process as solder ball attachment to a ball grid array (BGA) package.

In the first step, a transfer pin applies solder flux onto substrate contact pads. The solder balls are then picked and place on the substrate. Finally reflow for ball-to-substrate attachment.

Small solder balls 206 can be the same or a different material as solder balls 110. For example, Pb-free solder balls (Tin/silver/copper, tin/silver, etc.) can be used for both solder balls 206 and solder balls 110.

A flexible substrate, such as Upilex-S polyimide tape substrate or a stiff substrate such as BT core with weaved glass fiber cloth substrate, can be used as the interposer substrate 112. Both organic materials and inorganic materials such BT, FR4, ceramic, glass, silicon can be used. Examples include a laminated BT substrate, an Ajinomoto Film (ABF) build-up flip chip (FC) substrate, and a through silicon via interposer.

An advantage of using solder balls 206 for the interconnect terminals of interposer substrate 112 is that the conventional solder ball or solder bump attachment method can be used in the ball-to-substrate attachment manufacturing process. On the other hand manufacturing throughput of a bumped interposer substrate can be substantially higher than when conductor posts 118 are used due to a reduced number of processing steps. For example, photo imaging, photo masking and plating or chemical etching processes required for making a conductor posts 118 are not needed in a bumped substrate manufacturing processes. Moreover, the processing cost of attaching solder balls 206 to interposer substrate 112 is much lower than for attaching conductor posts 118.

Another important advantage of solder bumped substrate technology is that the height of the interconnect terminals can be two times higher or more than that of conductor posts 118. For example, a typical height of conductor posts 118 is approximately 25-45 μm in today's conductor post substrate technology shown by WO 2006/028090, published Mar. 16, 2006, entitled “Member for Interconnecting Wiring Films and Method for Producing the Same,” to Lijima et al., which is incorporated herein by reference in its entirety as though set forth in full below. In a solder ball attached interposer substrate, a solder ball height of 100 μm or more can be made using a conventional low cost manufacturing process.

An advantage of the package construction illustrated in FIG. 1 is that the vertical interconnection length between the bottom substrate 102 and components 122 is substantially shorter than the interconnection through a PCB. Since the interposer 112 has the shortest distance to the bottom substrate 102, the interposer substrate 112 provides a low-impedance signal transmission path to the bottom package. This interconnection path enables high speed communication between an IC die located in the bottom package (not shown in FIG. 1) and components 122 mounted on interposer substrate 112. The package construction in FIG. 1 provides a bottom substrate-to-top substrate high speed communication bus through the molded solder balls. Consequently, high speed communication between the bottom package and components 122 can be achieved.

As shown in FIG. 1, more than one component 122 can be mounted on interposer substrate 112. Different types of packages (flip chip, FBGA, etc.) can be mounted on the interposer substrate.

FIGS. 3A and 3B illustrate views of variations in the manner in which conductor posts 118 can be attached to solder balls 110. In FIG. 3A, a mold compound 320 a is truncated so that tops 308 of solder balls 110 a are flush with the top surface of mold compound 320 a. The mold compound 320 a can be sufficiently truncated such that the tops of solder balls 110 a are also removed to thereby form a circular solder pad flush with the top surface of mold compound 320 a. In a second embodiment shown in FIG. 3B, the top surface of mold compound 320 b is above the tops of solder balls 110. The top surface of mold compound 320 b is drilled or etched in the regions above solder balls 110 to form openings 302 so that conductor posts 118 of interposer substrate 112 will be received in openings 302 and make contact with solder balls 110.

The interposer substrate shown in FIGS. 1-3 has the same size as the bottom package. An interposer substrate with a size smaller than the bottom package can also be used. Additionally, more than one interposer substrate can be attached to the bottom package using the same method and steps discussed above.

FIG. 4A illustrates a view of a molded SiP (system in package) packaging construction. Both top 114 and bottom 116 surfaces (not numerically referenced in FIG. 4A) of interposer substrate 112 have direct electrical interconnection with first substrate 102 of the bottom package. On bottom surface 114 of interposer substrate 112, conductor posts 118 connect with first substrate 102 through the solder balls 110 in the bottom substrate package 102 at the contact pads on bottom substrate package top 106. On the top surface 116 of the interposer substrate, a wire bond 402 connects interposer substrate 112 with first substrate 102 along the exposed periphery of bottom package substrate 102. A second mold compound 406 a provides protection for the wire bond 402.

The following manufacturing steps can be used to make a SiP package shown in FIG. 4A. The interposer substrate is attached to bottom package first mold compound. The component(s) is mounted to the interposer substrate top. A wire bond connection between the interposer substrate and bottom package SiP. Finally, encapsulate the bond wires and component(s) on the interposer substrate with a second mold compound.

Alternatively, the sequence of the above assembly processes of attaching the interposer substrate to bottom package first mold compound and mounting the component(s) to the interposer substrate top can be exchanged by mounting components on the interposer substrate before the interposer substrate is attached to the bottom package mold top.

In a second mold process, bottom surface 116 of interposer substrate 112 can be partially exposed in the center (see FIG. 4B). Components 122 can be mounted to the interposer substrate top after second mold compound 406 b is used to encapsulate the wire bonds 402.

The following manufacturing steps can be used to make a SiP package shown in FIG. 4B. Attach an interposer substrate to a bottom package first mold compound. Then make a wire bond connection between the interposer substrate and bottom package substrate. Encapsulate the wire bonds and component(s) on the interposer substrate with a second mold compound. Finally mount the component(s) to the interposer substrate top.

Interposer substrate 412 c can have substantially the same size as first substrate 102 (see FIG. 4C). In this configuration, interposer substrate 112 top surface 416 c is not wire bonded to the bottom package.

FIG. 5A shows a closed 3-dimensional electrical potential surface formed by connecting the ground or power planes in both first substrate 102 and interposer substrate 112. The interconnection of the substrate planes separated by mold compound 120 is accomplished with an array of solder balls 510. Solder balls 510 can be substantially similar to solder balls 110. The IC die (or dies) of the bottom package 102 is enclosed within a 3-dimensional electrical potential enclosure 504 a comprising substrates 102 and 112 and grounded solder balls 510. This structure provides EMI emission protection by shielding electromagnetic radiation from as well as towards an IC die 506 inside the bottom package. For RF signal interconnection between the top and bottom packages, RF signal traces on the substrates at the top (interposer substrate 112) and the bottom (first 102) can be routed within the electrical potential enclosure to confine EMI emission within the enclosure. The 3-dimensional electrical potential enclosure is preferably maintained at ground or power potential. In other words, ground or power planes in the top and bottom substrates are preferred for the construction of the EMI shield enclosure. In addition, connecting the bottom package ground or power plane with solder balls 510 and the planes of interposer substrate 112 can improve heat spreading from the bottom package IC die and improve the thermal performance of the SiP 3D packaging structure. In addition to FIG. 5A, the 3D SiP interconnection design can be partitioned in various manners to separate digital from analog as well as various RF signals. For example, FIG. 5B shows that inner row(s) of molded small solder balls 510 b can be used to construct the 3-dimensional electrical ground potential enclosure within the SiP. Multiple electrical potential enclosures 504 b and 504 c can be constructed as shown in FIG. 5C.

FIG. 24 shows a further embodiment of an IC structure having multiple interposer substrates. More particularly, FIG. 24 shows at least two interposer substrates 2420 a and 2420 b. Each interposer substrate has a first or bottom surface 2440 a and 2440 b, respectively, and a second or top surface 2460 a and 2460 b, respectively. Similar to the single interposer substrate embodiments, each interposer substrate 2420 a and 2420 b has contact posts or pillars 2480 a and 2480 b, respectively, which make physical and electrical contact with solder balls or bumps 110 on bottom substrate 102. Various types of circuit components may be mounted on the multiple interposer substrates using wire bonding techniques (as shown for circuit component 2422 a) or solder post bonding techniques (as shown for circuit component 2422 b), or any other suitable mounting and connection technique. It will be apparent to anyone skilled in the relevant art that any number of interposer substrates may be mounted on the first substrate member. Further any number and type of circuit components (e.g., leadframe and BGA packages) may be mounted to each interposer substrate, depending on the needs of the circuit designers.

FIG. 6 shows a flowchart 600 providing example steps for assembling an IC package. Other structural and operational embodiments will be apparent to persons skilled in the relevant art(s) based on the following discussion. The steps shown in FIG. 6 do not necessarily have to occur in the order shown. The steps of FIG. 6 are described in detail below.

In step 602, an IC die is mounted to a first surface of a substrate. For example, in FIG. 7, an IC die 702 is coupled to a first-surface 704 of a substrate 706 using solder bumps 708.

In step 604, a first plurality of conductive elements is formed on the first surface of the substrate. For example, in FIG. 8, solder balls 802 are formed on first surface 704 of substrate 706.

In step 606, at least the IC die and the first surface of the substrate are encapsulated with an mold compound. For example, in FIG. 9, solder balls 802, IC die 702, and first surface 704 of substrate 705 are encapsulated in a mold compound 902. As shown in FIG. 9, solder balls 802 are completely encapsulated in mold compound 902. In another embodiment, however, portions of solder balls 802 may be exposed. For example, in the embodiment of FIG. 10, the tops of solder balls 802 are left exposed by mold compound 902.

As described above, the steps of flowchart 600 do not have to be completed in the order shown in FIG. 6. For example, in one embodiment, step 606 can be completed before step 604. For example, in FIG. 11, first surface 704 and IC die 702 can be encapsulated in a mold compound 1102. As shown in FIG. 11, via holes 1104 can formed mold compound 1102. In one embodiment, via holes 1104 can be formed in mold compound 1102 through a molding process where the mold chase is designed to have posts at the via holes locations preventing the molding compound from covering the certain regions (e.g., contact pads) on surface 704 of substrate 706. Alternatively, via holes 1104 can be formed after mold encapsulation by drilling through mold compound 1102 using a process such as laser drill or chemical etching. A first plurality of contact members can then be formed by filling the via holes with conductive material. For example, it. FIG. 12, solder paste 1202 fills via holes 1104 (not numerically referenced in FIG. 12) to create a first plurality of conductive elements.

In step 607, a portion of each of the first plurality of conductive elements is exposed. For example, in FIG. 13, the tops of solder balls 802 are exposed and truncated by removing a layer of mold compound 902. As shown in FIG. 13, truncated solder balls 802 form contact pads on the same plane of the remaining mold compound top surface.

In another embodiment, portions of solder balls 802 can be exposed by drilling through the mold compound. For example, in FIG. 15, holes 1502 are drilled into mold compound 902 to expose top portions of solder balls 802. Methods to drill through mold include such as mechanical drilling and chemical etching. Other drilling methods including laser ablation of the mold compound known in this field of art can also be used.

In an embodiment, step 607 can be optional. For example, in embodiments in which the encapsulation in step 606 is executed such that portions of the first plurality of conductive elements remain exposed, step 607 can be omitted. In another embodiment, a portion of the mold compound can be removed even when portions of the first plurality of conductive elements are exposed. For example, in the embodiment of FIG. 14, the tops of solder paste 1202 can be truncated by removing a layer of mold compound 1102. In doing so, a level surface is created on the top surface of mold compound. In alternate embodiments, a flat surface can be created by flattening the tops surfaces of the first plurality of conductive elements through, e.g., ball, post, or bump coning processes.

In step 608, a second plurality of conductive elements are on a second surface of an interposer substrate. In an embodiment, the second plurality of conductive elements can be a plurality of conductive posts. For example, in FIG. 16, conductive posts 1602 are formed on a surface 1604 of interposer substrate 1606. In another embodiment, the plurality of conductive elements can be a plurality of contact pads. For example, in FIG. 17, contact pads 1702 are formed on surface 1604 of interposer substrate 1606. Contact pads 1702 are substantially flush with surface 1604 of interposer substrate 1606.

In step 610, the first plurality of conductive elements are coupled to the second plurality of conductive elements. For example, in FIG. 18, conductive posts 1602 are coupled to solder balls 802. In doing so, electrical interconnection between interposer substrate 1606 and substrate 706 is established. As shown in FIG. 18, interposer substrate 1606 is placed on a flat surface formed by mold compound 902 and solder balls 802. In another embodiment, as described above, solder balls 802 can be exposed by drilling holes in the mold compound, thus, in the example of FIG. 19, conductive posts 1602 can be coupled respective ones of solder balls 802 through the holes formed in mold compound 902. In yet another embodiment, an adhesive can be used to facilitate the coupling process. For example, in FIG. 20, an adhesive layer 2002 (e.g., heat-activated adhesive) can be applied to surface 1604 to facilitate coupling between interposer substrate 1606 and the top surface of mold compound 902.

Moreover, as described above, solder paste filled into via holes can be used instead of solder balls for the first plurality of conductive elements. Thus, in the example of FIG. 21, conductive posts 1602 can be coupled to solder paste 1202, e.g., through a reflow process.

In another embodiment, as described above, contact pads can be used instead of conductive posts for the second plurality of conductive elements. Thus, in the example of FIG. 22, solder paste 1202 is coupled to contact pads 1702.

In step 612, at least one circuit member is mounted on a first surface of the interposer substrate. For example, passive components such as capacitors, inductors, electromagnetic coupling baluns, electromagnetic radiators, antennas, resistors, etc. can also be mounted on the first surface of the interposer substrate. For example, in FIG. 23, first and second circuit members 2302 and 2304 are coupled to surface 2306 of interposer substrate 1606.

Note that step 612 can be performed before step 610 where components or packages can be mounted onto the interposer substrate before the assembly is attached to the bottom package mold top. For example, passive components such as capacitors, inductors, electromagnetic coupling baluns, electromagnetic radiators, antennas, resistors, etc. can also be mounted on the top of interposer substrate 112.

Example Manufacturing and Assembly Embodiments

FIG. 25 shows a cross-sectional view of an IC package 2500. IC package 2500 includes first substrate 102, solder balls 108, interposer substrate 112, mold compound 120, electronic components 122, IC die 502, and solder balls 2502. First substrate 102, solder balls 108, and IC die 502 together form an embodiment of a device structure that is coupled to interposer substrate 112. IC package 2500 is similar to IC package 100 shown in FIG. 1 except that as described in further detail below, solder balls 2502 are formed as a combination of solder balls formed on interposer substrate 112 and solder balls formed on first substrate 102. As shown in FIG. 25, a gap 2504 is present between the top surface of mold compound 120 and the bottom surface of interposer substrate 112.

FIG. 26 shows a flowchart 2600 providing example steps for assembling an IC package. In one embodiment, flowchart 2600 provides a method of assembling an IC device by, inter alia, coupling an interposer substrate to a device structure. Other structural and operational embodiments will be apparent to persons skilled in the relevant art(s) based on the following discussion. The steps shown in FIG. 26 do not necessarily have to occur in the order shown. The steps of FIG. 26 are described in detail below.

In step 2602, a first plurality of solder balls is coupled to a first surface of an interposer substrate. For example, FIG. 27 shows an example embodiment of an interposer substrate 2700. As shown in FIG. 27, solder balls 2702 are coupled to surface 2704 of interposer substrate 2700. Moreover, a layer of flux material 2706 is also applied to surface 2704. In one embodiment, flux material 2706 can aide in coupling solder balls 2702 to surface 2704. For example, solder balls 2702 can be coupled to surface 2704 using a reflow process. In such an embodiment, flux material 2706 can be used to ensure that solder balls 2702 are coupled to the desired regions on surface 2704 (e.g., contact pads on surface 2704) and to enhance the electrical and mechanical connections between surface 2704 and solder balls 2702. After the reflow process is complete, flux material 2706 can be removed from surface 2704.

In step 2604, the interposer substrate is singulated. For example, FIG. 28 shows a strip of interposer substrates 2800. As shown in FIG. 28, strip 2800 includes eight interposer substrates 2802. Those skilled in the art will appreciate that strip 2800 is presented herein for illustration only and that strips of interposer substrates can include any number of interposer substrates. In the embodiment of FIG. 28, interposer substrates 2802 can be singulated along boundaries 2804. Interposer substrates 2802 may be singulated in a variety of ways. For example, methods for singulation include sawing, punching, abrasive particle cutting, and focused laser beam ablation cutting. FIG. 28 shows interposer substrates 2802 included in strip 2800. As would be appreciated by those skilled in the art based on the description herein, interposer substrates may also be included in blocks or panels. In an embodiment, a panel includes two or more strips, a strip includes two or more blocks, and a block includes four or more elements (e.g., interposer substrates) in a matrix configuration (e.g., 2×2 or 4×4).

Step 2604 is optional. For example, as described in greater detail below, interposer substrates 2802 can be laminated as a strip to respective device structures.

In step 2606, a second plurality of solder balls are coupled to contact members that are exposed at a surface of a device structure. For example, FIG. 29 schematically illustrates coupling a plurality of solder balls 2902 to solder balls 2904 of device structure 2900. In one embodiment, solder balls 2902 are placed on solder balls 2904. Next, the entire structure can be subject to a reflow process during which respective ones of solder balls 2902 and 2904 are joined. Coupling solder balls 2902 to solder balls 2904 increases the effective height of solder balls 2904. For example, in embodiments in which the conductive elements of an interposer substrate are relatively small (e.g., conductive posts or land grids), the height of the conductive elements in device structure 2900 (e.g., solder balls 2904) may be extended to enhance electrical interconnection between device structure 2900 and the interposer substrate.

Step 2606 is optional. For example, step 2606 may be omitted when the heights of the conductive elements of the interposer substrate and/or the device structure are sufficient to establish electrical interconnection between the two elements.

In step 2608, a non-conductive paste is applied to a surface of the interposer substrate or a surface of the device structure. For example, FIG. 30 shows a top view of a device structure 3000. As shown in FIG. 30, device structure 3000 has solder balls 3002 formed on its periphery. Moreover, a non-conductive paste 3004 is deposited in a central portion of the top surface of device structure 3000. In the embodiment shown in FIG. 30, non-conductive paste 3004 is applied in an “X” shape. However, as would be appreciated by those skilled in the art based on the disclosure herein, non-conductive paste 3004 may also be applied in other shapes.

Non-conductive paste 3000 can be used to fill a gap present between the interposer substrate and the device structure. For example, a gap may exist between the interposer substrate and the device structure because of the length of the conductive elements of either the interposer substrate or the device structure. Non-conductive paste 3004 can be used to fill this gap, thereby preventing damage to the device structure and/or the interposer substrate. In an embodiment, step 2608 is optional. For example, the non-conductive paste may not be used if no gap exists when the interposer substrate and the device structure are stacked.

In another embodiment, a non-conductive material can be applied as a film on either the interposer substrate or the device structure. For example, FIG. 31 shows a package 3100. Package 3100 is substantially similar to package 2500 shown in FIG. 25, except that package 3100 additionally includes film 3102 disposed between interposer substrate 112 and mold compound 120. As shown in FIG. 31, film 3102 fills gap 2504 in a central portion of package 3100. In an alternate embodiment, film 3102 completely fills gap 2504. Film 3102 can act as an adhesive that couples interposer substrate 112 to mold compound 120. Moreover, as shown in FIG. 31, film 3102 has a rectangular shape. However, in alternate embodiments, film 3102 can have a variety of other types of shapes (e.g., an “X” shape like non-conductive paste 3004 shown in FIG. 30).

In step 2610, the interposer substrate and the device structure are stacked. For example, FIG. 32 shows a cross-sectional diagram of a device structure 3202 stacked on an interposer 3204. Stacking the heavier device structure 3202 on interposer 3204, instead of vice versa, may enhance bonding because the weight of device structure 3202 effectively presses solder balls 3210 of device structure 3202 and solder balls 3220 of interposer substrate 3204 together.

In step 2612, the interposer substrate and the device structure are laminated. For example, FIG. 33 shows a strip of device structures 3300, according to an embodiment of the present invention. Strip 3300 includes three blocks of structures 3302. Each block 3302 includes four device structures 3304. Those skilled in the art will appreciate that the number of blocks in a strip and the number of structures in a block shown in FIG. 33 are provided for illustration purposes only. For example, in alternate embodiments, a strip may include four blocks each having sixteen device structures (e.g., in a 4×4 arrangement).

Each of device structures 3304 has a respective one of interposer substrates 3206 stacked thereon. As shown in FIG. 33, interposer substrates 3306 are singulated. However, in alternate embodiments, interposer substrates 3306 may be included in a strip of interposer substrates similar to, e.g., strip 2800 shown in FIG. 28. In still another embodiment, the interposer substrates and the device structures can both be singulated before lamination. In such an embodiment, interposer substrates and device structures can be laminated one at a time.

in one embodiment, device structures 3304 and interposer substrates 3306 can be laminated through a reflow process. However, reflow processes often result in the strip 3300 becoming warped. As a result, the interconnections between some of device structures 3304 and their respective interposer substrates 3306 can be damaged. Warpage can also cause loss of interconnection between some of device structures 3204 and respective interposer substrates 3306. To prevent warping, strip 3200 can be clamped during the reflow process. In another embodiment, weight(s) can be used to prevent warping. In such an embodiment, the thermal characteristics of the weight(s) can be factored into the reflow process. For example, because the weight(s) will absorb much of the heat used during the process, the reflow process may extended for a longer period of time and/or the temperature of the reflow process may be increased.

In another embodiment, thermal compression can be used to laminate device structures 3304 and interposer substrates 3306. In such an embodiment, strip 3300 and interposer substrates 3306 can be placed between two heated plates. In addition to applying heat to the interposer substrate and the device structure, the heated plates can apply pressure to reduce the time needed to complete the lamination. Additionally, the pressure can reduce warpage between device structures 3304 and interposer substrates 3306. Moreover, the plates can be raised to a relatively high temperature (e.g., compared to a reflow process), thereby further reducing the assembly time for an IC device.

In step 2614, the IC devices are singulated. For example, in FIG. 33, the IC devices that result from step 2612 can be singulated. The IC devices may be singulated in a variety of ways. For example, methods for unit singulation may include sawing, punching, abrasive particle cutting, and focused laser beam ablation cutting.

Conclusion

While various embodiments of the present invention have been described above, it should be understood that they have been presented by way of example only, and not limitation. It will be apparent to persons skilled in the relevant art that various changes in form and detail can be made therein without departing from the spirit and scope of the invention. Thus, the breadth and scope of the present invention should not be limited by any of the above-described exemplary embodiments, but should be defined only in accordance with the following claims and their equivalents. 

1. A method of manufacturing an integrated circuit (IC) package, comprising: stacking an interposer substrate and a device structure, wherein the interposer substrate has a first plurality of contact members formed on a first surface of the interposer substrate and wherein the device structure has a second plurality of contact members that are exposed at a surface of the device structure; and laminating the interposer substrate and the device structure such that the first plurality of contact members is physically and electrically coupled to the second plurality of contact members, wherein the interposer substrate is configured such that a circuit member mounted to a second surface of the interposer substrate is electrically coupled to the second plurality of contact members.
 2. The method of claim 1, further comprising: before the stacking, coupling a third plurality of contact members to the second plurality of contact members.
 3. The method of claim 2, wherein the third plurality of contact members comprises a plurality of solder balls.
 4. The method of claim 1, further comprising: before the stacking, applying a non-conductive paste on the surface of the device structure.
 5. The method of claim 1, further comprising: before the stacking, applying a non-conductive material in a film to at least one of the surface of the device structure or the first surface of the interposer substrate.
 6. The method of claim 1, further comprising: coupling the first plurality of contact members to the first surface of the interposer substrate.
 7. The method of claim 6, wherein the interposer substrate is included in a block of interposers substrate, the method further comprising: singulating the interposer substrate.
 8. The method of claim 1, wherein stacking comprises: stacking the device structure on top of the interposer substrate.
 9. The method of claim 1, wherein the device structure is included in a strip of device structures, the method further comprising: before the laminating, clamping the strip of device structures.
 10. The method of claim 1, wherein the device structure is included in a strip of device structures, the method further comprising: before the laminating, placing a weight on the strip of device structures.
 11. The method of claim 10, wherein laminating comprises heating the device structure and the interposer, wherein a time during which the device structure and interposer are heated is adjusted based on the presence of the weight.
 12. The method of claim 1, wherein the device structure is included in a strip of device structures, the method further comprising: after the laminating, singulating the device structure.
 13. The method of claim 1, wherein laminating comprises: inserting the interposer substrate and the device structure between heated plates.
 14. The method of claim 13, wherein laminating further comprises: applying pressure to the interposer substrate and the device structure through the heated plates.
 15. The method of claim 1, further comprising: before the stacking, applying a flux material to the surface of the device structure.
 16. The method of claim 1, wherein after the stacking, the first surface of the interposer substrate and the surface of the device structure is separated by a gap. 